That's a bloody good point, I vaguely remember being told that once (possibly in first year), but never really thought about it again.
Just done some reading and seems it's actually perfectly fine for digital signals (up to about 2 GPS anyway), but can be pretty devastating for analogue.
http://www.sigcon.com/Pubs/edn/bigbadbend.htm
http://www.ti.com/lit/ml/sloa089/sloa089.pdf
I haven't done any multilayer boards, but when I looked at Ant's design I did wonder about interference between the traces running on top of each other. Decided it probably wasn't going to be an issue on that board, however I didn't think at all about capacitance. That may have a much bigger impact. There's a method for calculating the parasitic capacitance in the second link there, might be worth working out what it would be and seeing what impact that would have on the design.